Passive or active pixel imagers are semiconductor devices capable of converting optical images into electronic signals. Pixels can be arranged in a matrix and utilized to generate video signals for video cameras, still photography, or anywhere incident radiation needs to be quantified. When incident radiation interacts with a photosite, charge carriers are liberated and collected for sensing. The amount of collected carriers in a photosite represents the amount of incident light collected for a given time period.
There are two basic devices with many variants, employed to collect and sense charge carriers in a photosite. These two basic devices are photodiodes and photogates. Variants of photodiode include, but are not limited to: Pinned, P-I-N, Metal-Semiconductor, Heterojunction and Avalanche. Photogate structures include: Charge Coupled Devices (CCD), Charge Injection Devices (CID) and their variants that include virtual phase, buried channel and other variations that utilize selective dopants. The selective dopants are used to control charge collection and transfer underneath and between the photogate(s) and the sense node.
FIG. 1 shows an exemplary prior art CID pixel arrangement with charge transfer electronics. Pixels 8 and 9 could be only two of a very long row of pixels that may contain hundreds or thousands of pixels. A row and column orientation has been given to the schematic contained herein. Depending on application requirements, the row and column orientation may be switched. Referring to FIG. 1, the CID pixel 8 may be described as a collection photogate 10 directly coupled to the sense photogate 12 by overlapping semiconductor layers. The semiconductor material is preferably polysilicon, but may be amorphous silicon, single crystal silicon, or other material. This overlap of the polysilicon layers provides a continuous path to control the flow of photon generated charge. This is accomplished by biasing the collection photogate opposite to the epitaxial layer 20 and similar to the substrate 22. A depleted area 14 is formed in the epitaxy under the collection photogate 10 by means of column bias 28. The sense photogate 12 is biased with half of the potential difference of the collection photogate relative to the epitaxy. As incident photons strike the pixel area and penetrate into the depleted region, they will be collected under the collection photogate site 10 as it has the greatest potential. The amount of charge an individual collection site can hold is dependent on the total capacitance that is due to the total area and the total potential difference between the collection photogate site and the sense photogate site. Therefore, a traditional CID device is limited to half of the total biasing limits allowed for a given silicon process. That is, a 1.2 micron CMOS process may be limited to 5.0 Volts total potential before circuit failure and therefore the maximum potential that can be used is 2.5 Volts for sensing photon generated charge. Either n-type or p-type epitaxial conductivity can be utilized; the difference being that the biasing requirements are similar but reversed in polarity. Reading the charge is accomplished through sense gate 12. The voltage on sense gate 12 forms depleted area 16. The sense gate voltage is amplified by amplifier 18. The amplifier output is thereafter processed further. Clearing the collected charge is accomplished by eliminating the potential bias on both collection and sense photogate sites through a reset gate 24 and reset bias voltage 26 applied through electrode 23 so that the charge held by the potentials is released and swept to the substrate layer 22 where the charge is drained by a fixed potential. Since the substrate layer is vertically below the collection and sense photogates of a CID, there is a direct path that doesn't block any of the photosensitive area. However, CID pixel separation is normally provided by a field oxide or nitride material that is relatively opaque to the shorter wavelengths.
Solid state imagers have been dominated by CCDs because of their low noise as compared to the alternatives such as Photodiodes and CIDs. The low noise advantage of CCD imagers is the result of collecting the photon generated charge at the pixel site and then coupling or shifting the actual charge to an amplifier at the periphery of the device. With a CID or Photodiode, the signal is collected and then sensed from the periphery of the array. The long polysilicon and metal busses degrade the signal with the associated resistance and capacitance. However, the low noise of the CCD causes the imager to be read in a fixed format and, once the charge is read, it is destroyed. The requirement of coupling the collected photon charge from the pixel to the periphery amplifier (a.k.a. Charge Transfer Efficiency), requires proprietary processing steps not compatible with industry standard CMOS or BiCMOS processes.
Solid State imaging devices have developed in parallel with CMOS technology. As a result, imager manufacturers had developed their own proprietary processes to maximize imager performance characteristics and wafer yield. Specialized silicon wafer processing have kept imager prices artificially high. Beginning in the early 90's the move to transfer the proprietary processes to industry standard CMOS processes was on. In both of the traditional photogate technologies, CID and CCD, the ability to collect and transfer the charge from the collection site to the sense site and the subsequent elimination of the collected charge is the fundamental readout sequence required. The original CCD and CID technology originally rely on the overlapping of polysilicon layers to provide a controlled path to transfer charge. Variants of photogates have utilized selective dopants to control the collection and transfer process. Modern submicron CMOS processes have no or very limited ability to provide a second polysilicon layer to control charge transfer.
A need exists for a pixel that can be utilized in an imaging device that doesn't require any extra implants or a second layer of polysilicon and is able to utilize the full biasing potential of submicron processes. A pixel designed without extra implants or a second polysilicon layer, will improve wafer yields due to decreased complexity, lower wafer processing costs, and improved pixel sensitivity, by eliminating double layers of polysilicon and/or implants that may block a photon's capture. Also, since submicron process have reduced operating biases, the total amount of charge that can be collected is also reduced. Smaller scale technology have heightened the need for a pixel that is able to utilize the full biasing potential of the process.